Apparatus and method for adjusting a rate at which data is transferred from a media access controller to a memory in a physical-layer circuit

ABSTRACT

A physical-layer circuit including a memory, a physical-layer device and a control circuit. The memory receives data from a media access controller (MAC) at a first rate. The MAC is separate from the physical-layer circuit. The physical-layer device receives the data from the memory and transmits the data from the physical-layer circuit to a peer device. The physical-layer device transfers the data from the memory to the peer device at a second rate. An amount of data stored in the memory is based on a difference between the first and second rates. The second rate is less than the first rate. The control circuit is connected between the memory and the physical layer device. The control circuit monitors the amount of the data stored in the memory and, based on the amount of the data stored in the memory, transmits a frame to the MAC to decrease the first rate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present disclosure is a continuation of U.S. patent application Ser. No. 14/047,533, filed on Oct. 7, 2013, which is a continuation of U.S. patent application Ser. No. 11/696,476 (now U.S. Pat. No. 8,553,720), filed on Apr. 4, 2007, which claims the benefit of U.S. Provisional Application No. 60/793,118 filed on Apr. 19, 2006. The entire disclosures of the applications referenced above are incorporated herein by reference.

BACKGROUND

The present invention relates generally to data communications. More particularly, the present invention relates to adaptive speed control for interfaces between media access controllers (MAC) and physical-layer devices (PHY).

SUMMARY

A first network device is provided and includes a host, a memory, a media access controller, a physical-layer device, and a control circuit. The media access controller is configured to (i) receive data from the host, and (ii) store the data in the memory at a first rate. The physical-layer device configured to (i) receive the data from the memory, and (ii) transmit the data from the first network device to a second network device. The memory is connected between the media access controller and the physical-layer device. An amount of the data stored in the memory is based on (i) the first rate at which the media access controller stores the data from the host in the memory, and (ii) a second rate at which the physical-layer device transfers the data from the memory to the second network device. The first rate is greater than the second rate. The control circuit configured to (i) monitor the amount of the data stored in the memory, and (ii) based on the amount of the data stored in the memory, transmit a first frame to the media access controller. The media access controller is configured to, in response to the first frame, decrease the first rate at which the media access controller transfers the data from the host to the memory.

In other features, a method is provided for adjusting a rate at which data is transferred from a media access controller to a memory. The memory is connected between the media access controller and a physical layer device. Each of the media access controller, the memory, and the physical layer device are implemented in a first network device. The method includes: receiving data from a host at the media access controller, where the host is also implemented in the first network device; storing, via the media access controller, the data in the memory at a first rate; transferring the data stored in the memory to the physical-layer device; and transmitting, from the first network device to a second network device via the physical-layer device, the data transferred to the physical layer device. The data is transferred to the physical layer device is transmitted, at a second rate, by the physical layer device to the second network device, wherein the second rate is less than the first rate. An amount of the data stored in the memory is monitored. The amount of the data stored in the memory is based on each of the first rate and the second rate. Based on the amount of the data stored in the memory, a first frame is transmitted to the media access controller. In response to the first frame, the first rate at which the media access controller transfers the data from the host to the memory is decreased.

In general, in one aspect, the invention features an apparatus comprising: a first first-in first-out buffer (FIFO) to receive and store data from a media access controller (MAC); a physical-layer device (PHY) to transmit a signal representing the data; and a control circuit comprising a read circuit to transfer the data from the first FIFO to the PHY, and a transmit pause circuit to transmit a pause frame to the MAC when an amount of the data stored in the first FIFO exceeds a predetermined threshold.

In some embodiments, the pause frame comprises a IEEE 802.3x pause frame. Some embodiments comprise an integrated circuit comprising the apparatus. Some embodiments comprise the MAC. In some embodiments, the MAC comprises a 10 Gbps single-speed MAC, the PHY comprises a quad-speed PHY having speeds of 10 Mbps, 100 Mbps, 1 Gbps, and 10 Gbps, and the MAC and the PHY communicate over a single-speed interface. In some embodiments, the single-speed interface comprises a XAUI interface. Some embodiments comprise a network device comprising the apparatus. In some embodiments, the network device is selected from the group consisting of: a network switch; a router; and a network interface controller. In some embodiments, the control circuit further comprises: a receive pause circuit to pause the transfer of the data from the first FIFO to the PHY when the PHY receives a second signal representing a second pause frame. In some embodiments, the second pause frame comprises a IEEE 802.3x pause frame. In some embodiments, the PHY receives signals representing frames of data sent by a peer device; and wherein the control circuit drops one or more of the frames of data. Some embodiments comprise management information base (MIB) drop counter to count the dropped frames of the data. Some embodiments comprise a second FIFO to store frames of data received by the PHY from a peer device; wherein the control circuit retrieves the frames of data from second FIFO, and transmits the frames of data to the MAC. In some embodiments, the read circuit transfers the data from the first FIFO to the PHY again when needed in half-duplex mode. In some embodiments, the PHY receives a pause frame from the MAC and transmits a signal representing the pause frame.

In general, in one aspect, the invention features an apparatus comprising: first buffer means for receiving and storing data from a media access controller (MAC); physical-layer means for transmitting a signal representing the data; and means for controlling comprising read means for transferring the data from the first buffer to the physical-layer means, and transmit pause means for transmitting a pause frame to the MAC when an amount of the data stored in the first buffer exceeds a predetermined threshold.

In some embodiments, the pause frame comprises a IEEE 802.3x pause frame. Some embodiments comprise an integrated circuit comprising the apparatus. Some embodiments comprise the MAC. In some embodiments, the MAC comprises a 10 Gbps single-speed MAC, the physical-layer means comprises a quad-speed physical-layer means having speeds of 10 Mbps, 100 Mbps, 1 Gbps, and 10 Gbps, and the MAC and the physical-layer means communicate over a single-speed interface. In some embodiments, the single-speed interface comprises a XAUI interface. Some embodiments comprise a network device comprising the apparatus. In some embodiments, the network device is selected from the group consisting of: a network switch; a router; and a network interface controller. In some embodiments, the means for controlling further comprises: receive pause means for pausing the transfer of the data from the first buffer to the physical-layer means when the physical-layer means receives a second signal representing a second pause frame. In some embodiments, the second pause frame comprises a IEEE 802.3x pause frame. In some embodiments, the physical-layer means receives signals representing frames of data sent by a peer device; and wherein the means for controlling drops one or more of the frames of data. Some embodiments comprise means for counting the dropped frames of the data. Some embodiments comprise second buffer means for storing frames of data received by the physical-layer means from a peer device; wherein the means for controlling retrieves the frames of data from the second buffer means, and transmits the frames of data to the MAC. In some embodiments, the read circuit transfers the data from the first FIFO to the physical-layer means again when needed in half-duplex mode. In some embodiments, the physical-layer means receives a pause frame from the MAC and transmits a signal representing the pause frame.

In general, in one aspect, the invention features a method comprising: storing data received from a media access controller (MAC) at a first data rate; retrieving the stored data at a second data rate; generating a signal representing the retrieved data; and generating a pause frame when an amount of the stored data exceeds a predetermined threshold.

Some embodiments comprise receiving the data from the MAC. Some embodiments comprise transmitting the pause frame to the MAC. In some embodiments, the pause frame comprises a IEEE 802.3x pause frame. Some embodiments comprise receiving signals representing frames of data sent by a peer device; and dropping one or more of the frames of data. Some embodiments comprise counting the dropped frames of data. Some embodiments comprise receiving signals representing frames of data sent by a peer device; storing the frames of data in a buffer; retrieving the frames of data from the buffer; and transmitting the frames of data to the MAC. Some embodiments comprise pausing the retrieving of the data when a second signal representing a second pause frame is received. In some embodiments, the second pause frame comprises a IEEE 802.3x pause frame. Some embodiments comprise generating the signal representing the retrieved data again when needed in half-duplex mode. Some embodiments comprise receiving a pause frame from the MAC; and transmitting a signal representing the pause frame.

In general, in one aspect, the invention features a computer program executable on a processor, comprising: instructions for storing data received from a media access controller (MAC) at a first data rate; instructions for retrieving the stored data at a second data rate; wherein a physical-layer device to generate a signal representing the retrieved data; and instructions for generating a pause frame when an amount of the stored data exceeds a predetermined threshold.

Some embodiments comprise instructions for transmitting the pause frame to the MAC. In some embodiments, the pause frame comprises a IEEE 802.3x pause frame. Some embodiments comprise, wherein signals are received representing frames of data sent by a peer device, instructions for dropping one or more of the frames of data. Some embodiments comprise instructions for counting the dropped frames of data. Some embodiments comprise, wherein signals are received representing frames of data sent by a peer device, instructions for storing the frames of data in a buffer; instructions for retrieving the frames of data from the buffer; and wherein the frames of data are transmitted to the MAC. Some embodiments comprise instructions for pausing the retrieving of the data when a second signal representing a second pause frame is received. In some embodiments, the second pause frame comprises a IEEE 802.3x pause frame. Some embodiments comprise instructions for generating the signal representing the retrieved data again when needed in half-duplex mode.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a data communication system comprising a network device in communication with a peer network device according to some embodiments of the present invention.

FIG. 2 shows a process for the data communications system of FIG. 1 according to some embodiments of the present invention.

The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears.

DESCRIPTION

In conventional data communications systems, a multi-speed media access controller (MAC) is generally connected to a multi-speed physical-layer device (PHY) by a multi-speed interface. In such systems, the PHY speed is set by auto-negotiation, software, or the like, and the MAC adapts its speed accordingly.

However, in some systems, the MAC may not support all the data rates supported by the PHY, or vice versa. For example, when a single-speed MAC is connected by a single-speed interface to a multi-rate PHY, the PHY may operate at a speed that is not supported by the MAC. As another example, even though the MAC and PHY are both multi-speed, either may support a speed not supported by the other.

Embodiments of the present invention provide adaptive speed control for MAC-PHY interfaces. According to these embodiments, a first-in first-out buffer (FIFO) buffers data sent from the MAC to the PHY, and a control circuit sends a pause frame to the MAC when the amount of data in the FIFO exceeds a predetermined threshold. Flow control can be enabled in the MAC according to IEEE standard 802.3x, and each pause frame can comprise an IEEE 802.3x pause frame.

Flow control with peer devices can be implemented by the control circuit. For example, the control circuit auto-negotiates with peer devices to implement flow control according to IEEE standard 802.3x. When the control circuit receives a pause frame from a peer device, the control circuit pauses the flow of data from the FIFO to the PHY.

FIG. 1 shows a data communication system 100 comprising a network device 102 in communication with a peer network device 104 according to some embodiments of the present invention. Network device 102 comprises a host 106 in communication with a media access controller (MAC) 108, which is in communication with a physical-layer circuit 110, which is in communication with peer network device 104. Physical-layer circuit 110 comprises a transmit first-in first-out buffer (FIFO) 112, a control circuit 114, and a physical-layer device (PHY) 116. Control circuit 114 comprises a read circuit 118, a receive pause circuit 120, and a transmit pause circuit 122. MAC 108 can comprise a plurality of conventional management information base (MIB) counters 124. A MIB is a database used to manage network communication devices, as is well-known in the relevant arts. Physical-layer circuit 110 can comprise a MIB drop counter 126 to count dropped frames.

Physical-layer circuit 110 can also include a receive FIFO 128 to buffer data received from peer network device 104. That is, receive FIFO 128 stores frames of data received by PHY 116 from peer network device 104, and control circuit 114 retrieves the frames of data from receive FIFO 128 and transmits the frames of data to MAC 108. Because the data rate of MAC 108 exceeds the data rate of PHY 116, all or nearly all of each frame should be stored in receive FIFO 128 before transmitting the frame to MAC 108 to prevent underrun of receive FIFO 128.

Network device 102 can be implemented as a switch, router, network interface controller (NIC), and the like. Physical-layer circuit 110 can be implemented as one or more integrated circuits.

In some embodiments, MAC 108 is a 10 Gbps single-speed MAC, PHY 116 is a quad-speed PHY having speeds of 10 Mbps, 100 Mbps, 1 Gbps, and 10 Gbps, and MAC 108 and physical-layer circuit 110 communicate over a single-speed interface such as XAUI. In other embodiments, MAC 108 is a multi-speed MAC that communicates with physical-layer circuit 110 over a multi-speed interface.

FIG. 2 shows a process for data communications system 100 of FIG. 1 according to some embodiments of the present invention. Although in the described embodiments, the elements of process 200 are presented in one arrangement, other embodiments may feature other arrangements, as will be apparent to one skilled in the relevant arts based on the disclosure and teachings provided herein. For example, in various embodiments, some or all of the steps of process 200 can be executed in a different order, concurrently, and the like.

When network device 102 boots up, flow control is enabled for MAC 108 (step 202), and control circuit 114 can auto-negotiate with peer network device 104 to establish flow control (step 204). The flow control mechanism can be IEEE 802.3x flow control.

MAC 108 receives frames of data from host 106 to be transmitted to peer network device 104 (step 206), and transmits the data to physical-layer circuit 110 (step 208), which stores the data in FIFO 112 as it is received (step 210). Read circuit 118 transfers the data from FIFO 112 to PHY 116 at the data rate required by PHY 116 (step 212). PHY 116 transmits a signal representing the data to peer network device 104 (step 214).

Control circuit 114 monitors the amount of data stored in FIFO 112 (step 216). Because the data rate of MAC 108 exceeds the data rate of PHY 116, the amount of data stored in FIFO 112 will increase. When the amount of data stored in FIFO 112 exceeds a predetermined threshold (step 218), transmit pause circuit 122 transmits a pause frame to MAC 108 (step 220). The pause frame can be a IEEE 802.3x pause frame, and IEEE 802.3x flow control is always enabled for MAC 108. Therefore, MAC 108 stops transmitting data to physical-layer circuit 110 for the interval specified by the pause frame (step 222).

In some cases, control circuit 114 and peer network device 104 auto-negotiates to implement flow control. Control circuit 114 monitors traffic received from peer network device 104 for the presence of pause frames (step 224). When control circuit 114 determines that a pause frame has been received from peer network device 104 (step 226), read circuit 118 pauses the transfer of data from FIFO 112 to PHY 116 for the interval specified by the received pause frame (step 228). The pause frame is not transferred to MAC 108.

Because flow control is always enabled for MAC 108, MAC 108 may generate pause frames. When physical-layer circuit 110 receives a pause frame from MAC 108, PHY 116 simply transmits a signal representing the pause frame to peer network device 104. In some embodiments, control circuit 114 is also responsible for half-duplex and retransmission if needed. That is, read circuit 118 transfers data from FIFO 112 to PHY 116 again when needed in half-duplex mode, for example following a collision during transmission by PHY 116 of a signal representing the data.

When flow control is disabled with peer network device 104, physical-layer circuit 110 can drop frames of data received from peer network device 104. Because the frames are dropped in physical-layer circuit 110, the drops will not be recorded by MIB counters 124 in MAC 108. Therefore, in some embodiments, physical-layer circuit 110 comprises a MIB drop counter 126 to count the dropped frames.

Embodiments of the invention can be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Apparatus of the invention can be implemented in a computer program product tangibly embodied in a machine-readable storage device for execution by a programmable processor; and method steps of the invention can be performed by a programmable processor executing a program of instructions to perform functions of the invention by operating on input data and generating output. The invention can be implemented advantageously in one or more computer programs that are executable on a programmable system including at least one programmable processor coupled to receive data and instructions from, and to transmit data and instructions to, a data storage system, at least one input device, and at least one output device. Each computer program can be implemented in a high-level procedural or object-oriented programming language, or in assembly or machine language if desired; and in any case, the language can be a compiled or interpreted language. Suitable processors include, by way of example, both general and special purpose microprocessors. Generally, a processor will receive instructions and data from a read-only memory and/or a random access memory. Generally, a computer will include one or more mass storage devices for storing data files; such devices include magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and optical disks. Storage devices suitable for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM disks. Any of the foregoing can be supplemented by, or incorporated in, ASICs (application-specific integrated circuits).

A number of implementations of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other implementations are within the scope of the following claims. 

What is claimed is:
 1. A physical-layer circuit comprising: a memory to receive data from a media access controller at a first rate, wherein the media access controller is separate from the physical-layer circuit; a physical-layer device to (i) receive the data from the memory, and (ii) transmit the data from the physical-layer circuit to a peer device, wherein the physical-layer device transfers the data from the memory to the peer device at a second rate, wherein an amount of data stored in the memory is based on a difference between the first rate and the second rate, and wherein the second rate is less than the first rate; and a control circuit coupled to the memory and the physical layer device, wherein the control circuit is to (i) monitor the amount of the data stored in the memory, and (ii) based on the amount of the data stored in the memory, transmit a first frame to the media access controller to decrease the first rate at which the media access controller transfers the data to the memory.
 2. The physical-layer circuit of claim 1, wherein the first frame indicates a pause interval during which the media access controller is to temporarily cease transferring of the data to the memory.
 3. The physical-layer circuit of claim 1, wherein the control circuit is further to (i) determine whether the amount of the data stored in the memory has exceeded a predetermined threshold, and (ii) transmit the first frame to the media access controller in response to the amount of the data stored in the memory having exceeded the predetermined threshold.
 4. The physical-layer circuit of claim 1, wherein: the physical-layer device is further to receive a second frame from the peer device; and the control circuit is further to, in response to the second frame, pause transfer of the data from the memory to the physical-layer device.
 5. A network device comprising: the physical-layer circuit of claim 1; and the media access controller, wherein the media access controller is to, in response to receiving the first frame from the control circuit, decrease the first rate at which the media access controller transfers the data to the memory.
 6. The network device of claim 5, further comprising a host, wherein: the host transfers the data to the media access controller prior to the media access controller transferring the data to the memory; and the media access controller, the memory, the physical-layer device, and the control circuit are implemented on an integrated circuit.
 7. The network device of claim 6, wherein the media access controller is further to stop storing the data from the host in the memory in response to the first frame.
 8. The network device of claim 5, wherein the media access controller is further to stop storing the data in the memory for an interval of time specified in the first frame.
 9. The network device of claim 5, wherein: the media access controller is a single-speed media access controller; and the physical-layer device is a quad-speed physical-layer device having a plurality of speeds.
 10. The network device of claim 5, wherein the media access controller is further to operate at (i) the first rate while the physical-layer device is operating at the second rate, and (ii) a third rate while the physical-layer device is operating at a fourth rate.
 11. The network device of claim 10, wherein: the third rate is greater than 0 and less than the first rate; and the fourth rate is greater than 0 and less than the second rate.
 12. A method of operating a physical-layer circuit, wherein the physical-layer circuit comprises a memory, a control circuit and a physical-layer device, and wherein the control circuit is coupled to the memory and the physical layer device, the method comprising: receiving data at the memory from a media access controller, wherein the data is received at the memory at a first rate, and wherein the media access controller is separate from the physical-layer circuit; receiving the data from the memory at the physical-layer device; transmitting the data from the physical-layer circuit to a peer device, wherein physical-layer device transfers the data from the memory to the peer device at a second rate, wherein an amount of data stored in the memory is based on a difference between the first rate and the second rate, and wherein the second rate is less than the first rate; monitoring the amount of the data stored in the memory; and based on the amount of the data stored in the memory, transmitting a first frame from the control circuit to the media access controller to decrease the first rate at which the media access controller transfers the data to the memory.
 13. The method of claim 12, wherein the first frame indicates a pause interval during which the media access controller is to temporarily cease transferring of the data to the memory.
 14. The method of claim 12, further comprising determining whether the amount of the data stored in the memory has exceeded a predetermined threshold, wherein the transmitting of the first frame to the media access controller is performed in response to the amount of the data stored in the memory having exceeded the predetermined threshold.
 15. The method of claim 12, further comprising: receiving a second frame from the peer device at the physical-layer device; and in response to the second frame, pausing transfer of the data from the memory to the physical-layer device.
 16. The method of claim 12, wherein: the media access controller is a single-speed media access controller; and the physical-layer device is a quad-speed physical-layer device having a plurality of speeds.
 17. The method of claim 12, wherein: the media access controller is further to operate at (i) the first rate while the physical-layer device is operating at the second rate, and (ii) a third rate while the physical-layer device is operating at a fourth rate; the third rate is greater than 0 and less than the first rate; and the fourth rate is greater than 0 and less than the second rate.
 18. The method of claim 12, further comprising ceasing to store, via media access controller, the data in the memory for an interval of time specified in the first frame.
 19. The method of claim 12, further comprising transferring the data from a host to the media access controller prior to the media access controller transferring the data to the memory, wherein the media access controller, the memory, the physical-layer device, and the control circuit are implemented on an integrated circuit.
 20. The method of claim 19, further comprising ceasing to store, via the media access controller, the data from the host in the memory in response to the first frame. 